Simulation and Design of a PIC-Based Heterodyne Optical Phase Locked Loop

Abstract

In this paper, we report on our simulation and design of a photonic integrated circuits (PIC)-based heterodyne optical phase-locked loop (OPLL). Our simulation reveals that the OPLL operation can be in one of three states, i.e., absolutely stable, metastable, and unstable states, depending on the relative position of the initial phase reversal point to the loop bandwidth. By systematically optimizing all of the loop parameters involved, the loop bandwidth of 247.8 MHz and the residual phase noise variance of 0.012 rad2 are theoretically obtained in such a PIC-OPLL system, which are better than any reported counterparts. In addition, the lowest required power of the master laser is also evaluated, assuming that the largest acceptable residual phase noise variance is 0.02 rad2, and it is found that the lowest master laser power is −54 dBm in our current OPLL system, and this value can be reduced to −56 dBm, providing that the summed linewidth is reduced to 10 kHz.