Simulation and Analysis of Hybrid Ultra Dense Memory Cell by Using Single Electron Transistor

Abstract

In VLSI Technology, Integration Density of memory requirements have reached in tera byte. The basic element to design any type of memory array is memory cell. To design a memory array, selective read and write memory cells are most important. The most promising application of single electronic devices is the Single Electron Memory cell. Here, we propose to design a memory cell using single electron transistor. The working depends upon the coulomb blockade phenomenon, in which electrons are tunneled one by one through the channel. Basic single electron cell are utilized throughout the work as electron trap. The hybrid electron trap memory is directly utilized to design a random access memory array. Information storage is due to the presence or absence of single electron at island. The paper gives a new dimension to make a different memory cell by using a hybrid multi island junction. The operation of proposed circuits are verified in Monte Carlo Simulator Tool SIMON2 (Simulation of nanoelectronics device) which is a simulator for single electron tunnel circuits and devices. The stability diagram is verified by the functioning of the circuits.