Simulating macroscale brain circuits with microscale resolution

Abstract

Event Abstract Back to Event Simulating macroscale brain circuits with microscale resolution Susanne Kunkel1*, Tobias C. Potjans2, 3, Abigail Morrison4 and Markus Diesmann1, 3, 4 1 Bernstein Center for Computational Neuroscience, Germany 2 Research Center Jülich, Germany 3 RIKEN Computational Science Research Program, Japan 4 RIKEN Brain Science Institute, Japan Thanks to distributed computing techniques, today it is possible to routinely simulate local cortical networks of around 105 neurons with up to 109 synapses on clusters and multiple processor shared memory machines. Simulations of this type carried out with NEST [1] scale well up to at least 1000 processors. However, simulations of microscale networks corresponding to approximately 1mm3 of the cortex are limited in their explanatory power. To understand the functions of the brain, we need to simulate macroscale circuits involving multiple interacting areas [2]. One approach is to develop brain-scale networks (see Figure) in which the individual nodes are realized by microcircuits at the resolution of point neurons and synapses such as the layered local cortical network model we recently developed [3]. These networks will be one or two orders of magnitude larger than the previously studied models not only in terms of numbers of neurons and synapse but also in terms of computational load.This presents a number of challenges to current simulation technology. Firstly, as the number of processors increases, the memory overhead due to serial data structures eventually dominates the total memory usage and so limits the parallelization. An example of this is the usage of proxies representing remote neurons on each machine and providing an interface to the local neurons. Although such representations of remote neurons require much less memory than local neurons, their proportion of the total neuronal memory usage approaches one as the number of machines increases. Secondly, the size of the maximal synaptic delay determines the size of the spike buffers each neuron uses to queue incoming spikes [4]. For local networks these buffers are small, as the synaptic delays are in the order of milliseconds. If interacting brain areas are to be considered, the synaptic delays increase by an order of magnitude, which entails a corresponding increase of memory usage for the spike buffers. It is also important that a distinction can be made between the axonal and the dendritic components of synaptic delays, as this affects the behavior of plasticity models dependent on relative spike timing [5,6]. We quantify the effects of these memory limitations in our application up to the order of 10k processors and present strategies for addressing these problems.Next-Generation Supercomputer Project of MEXT, EU Grant 15879 (FACETS), BMBF Grant 01GQ0420, Helmholtz Alliance on Systems Biology INCF-09-46