Simulating Analysis of Dynamic Responses for CSP under Board Level Drop Test

Abstract

Along with the more and more use of portable electronic products, such as mobile phones and PDA, the drop impact performance of solder joints for CSP is a critical concern to semiconductor and electronic product manufacturers. This problem is more serious with the application of lead free soldering, because compared with the traditional SnPb solder alloy, lead free solder alloy have higher rigidity and lower ductibility, and the traditional drop test is high cost and time consuming, and it is quite difficult to observe the full dynamic responses during the drop impact. Aim at this problem, ANSYS/LS-DYNA is employed and a three-dimensional quarter model with 15 representatives lead free TFBGA mounted at PCB is developed to simulate the board level drop test. In this model, die, adhesive, solder mask, and pad are taken into account. The pad definition is NSMD (non-solder mask defined) on PCB side according to the JEDEC standard (JESD22-B111) and effects of two different pads design on package side are considered by modeling. The full dynamic drop process of the model are simulated, and further dynamic response curves of PCB and solder joints are generated and analyzed, including the velocity, stress-strain curve, bending and so on. From the dynamic responses, the normal stress of solder joint shows cyclic with the amplitude decreased gradually as PCB bends down and up during the process of drop impact. The results generated from the current model are in good agreement with other researchers' experimental results, namely, the normal stress is the dominant failure indicator of solder joint when it is used to compare with the same or similar boards, which is proven by professor Tee. So the normal stress criterion is applied to predict the potential failure locations of solder joints during the drop impact