Simulated Annealing Based Temperature Aware Floorplanning

Abstract

Power density of microprocessors is increasing with every new process generation resulting in higher maximum chip temperatures. The high temperature of the chip greatly affects its reliability, raises the leakage power consumed to unprecedented levels, and makes cooling solutions significantly more expensive. The maximum temperature of a block in a chip depends not only on its own power density, but also on the power density of the adjacent blocks. Consequently, the placement of architectural blocks, or a particular floorplan selected for a given chip, can considerably affect the maximum temperature of the chip. This paper analyzes the impact of floorplanning on the maximum temperature by using as examples the Alpha and Pentium Pro microprocessors. We show that the difference between the maximum temperatures of two different floorplans can be as high as 37 � C. We have modified a simulated annealing-based floorplanning tool to include temperature as an objective for block placement to reduce the hot spot temperature. We show that it is possible to find a floorplan that can reduce the maximum temperature of a chip by up to 21 � C compared to the original floorplan while maintaining comparable performance.