Simplified Three-Level Five-Phase SVPWM

Abstract

A simplified space vector pulse width modulation (SVPWM) is proposed for a three-level five-phase inverter. The proposed method generates the duty cycle of the three-level inverter switches based on dwell times of the two-level inverter and carrier index. The proposed method automatically determines the eligible vectors, region, and switching sequence of optimized five vectors based on the modulation index. Out of 243 available vectors, 113 most eligible vectors are used for generation of desired voltage reference in main subspace, while zeroing the average voltage in the auxiliary subspace by using the proper switching sequence. This method also uses the redundant vectors in each subcycle thus balances the dc-link capacitor voltages and no additional algorithm or techniques are needed to balance the dc-link capacitor voltage. The identification of the reference location with the carrier index using the signum function simplifies the algorithm implementation. Thus, the proposed method eases the implementation of optimum five vectors to a greater extent. Based on only changing the carrier index, the proposed method can be easily extended for any multiphase multilevel (5, 7,…, n) inverter. The simulation and hardware results of the three-level five-phase inverter validate the proposed simplified method.