Simplified full precision offset estimation for timing and frequency synchronisation using factorised FFT processor

Abstract

This paper presents a design methodology for highly reliable timing and frequency synchronisation through scaled floating point arithmetic-based factorised FFT processor. Radix factorisation is the main technique for achieving high energy efficiency, followed by errorless floating point arithmetic computation will increase the performance of the coarse timing and frequency synchronisation. Here representation of error propagation model for training sequence used for synchronisation process with fixed point arithmetic is derived to analyse the rounding effect. The effect of quantisation loss due to the fixed point arithmetic errors and in overall OFDM system performance with decimation-in-frequency (DIF) FFT configuration is analysed and compared with full precision floating arithmetic through simulation. Based on the results, a simple bit size optimisation is proposed to yield full precision accuracy with fewer bits. Finally radix-22 algorithm is proposed to compensate the area overhead due to inclusion of precision arithmetic in FFT computation.