Simplification of boolean verification conditions

Abstract

The correctness problem for hardware and software systems can often be reduced to the validity problem for propositional or predicate logic. However, the size of the formulas to be validated grows faster than the size of the system under investigation, and the complexity of the validation procedure makes this approach practically intractable for large programs. We introduce a strategy for dealing with this problem in the propositional case, corresponding, e.g. to digital circuits and concurrent synchronization algorithms. Efficiently computable criteria are used to assess the mutual relevance of formulas and subformulas. They are based on the notions of interpolation and polarity, and allow to detect and discard provably irrelevant parts of boolean verification conditions. These criteria lead to a simplification and validation method, whose efficiency is investigated both theoretically and practically.