Abstract
An optimising method to improve the speed of a source-coupled-logic static frequency divider is presented. A piecewise linear transistor model is applied to simplify the large-signal analysis. The optimised circuit parameters can be quickly estimated from the analysis result. The simulation and measurement results on a 0.35 mum CMOS process have been used to demonstrate this optimisation method
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have