Simple generation of threshold for images binarization on FPGA

Egidio Ieno,Luis Manuel Garcés,Alejandro José Cabrera,Tales Cleber Pimenta

doi:10.15446/ing.investig.v35n3.51750

Abstract

This paper proposes the FPGA implementation of a threshold algorithm used in the process of image binarization by simple mathematical calculations. The implementation need only one image iteration and its processing time depends on the size of the image. The threshold values of different images obtained through the FPGA implementation are compared with those obtained by Otsu’s method, showing the differences and the visual results of binarization using both methods. The hardware implementation of the algorithm is performed by model-based design supported by the MATLAB®/Simulink® and Xilinx System Generator® tools. The results of the implementation proposal are presented in terms of resource consumption and maximum operating frequency in a Spartan-6 FPGA-based development board. The experimental results are obtained in co-simulation system and show the effectiveness of the proposed method.

Highlights

Image analysis usually refers to processing of images with the goal of finding what objects are presented in the image
The image processing is implemented by the Xilinx System Generator® (XSG) using model-based design techniques in MATLAB®/Simulink® software
In this paper an algorithm to calculate the threshold for image binarization using simple mathematical calculations over a 3x3 window was proposed

Summary

Introduction

Image analysis usually refers to processing of images with the goal of finding what objects are presented in the image. One of the most widely used techniques for segmenting the objects in an image is binarization In this technique, each pixel is compared to a threshold separating the foreground and background in an image. The output of the thresholding operation is a binary image. The uses of a bi-level information decrease. How to cite: Ieno, E., Garcés, L.M., Cabrera, A.J., & Pimenta, T.C. Simple generation of threshold for images binarization on FPGA.

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