Simple expressions for interconnection delay, coupling and crosstalk in VLSI's

Abstract

RC interconnection delay is one of the most essential issues in recent VLSIs. A closed-form formula for a waveform of the RC line with practical boundary conditions is derived. Expressions are also derived for a voltage slope and transition time of the RC interconnection. Other important issues related to interconnections are capacitive coupling of two lines and a crosstalk induced by the capacitive coupling. Expressions are derived for a coupling capacitance and a crosstalk voltage height, which can be used in VLSI designs. Using the expression, optimum line width which minimizes RC delay is discussed. >