Silicon Nitride Thickness Profile Tuning to Reduce Shallow Trench Isolation Variability in Planar CMOS

Abstract

A method for low pressure chemical vapor deposition of silicon nitride that utilizes thermal ramping during multiple deposition steps is demonstrated in a 300 mm vertical batch reactor. Temperature ramp rates in each heater zone are optimized to deposit silicon nitride films with edge-thin (or dome-shape) thickness profiles across the length of the reactor. This process is compatible with real-time automated tuning schemes commonly used to control thickness across all reactor zones. No significant film degradation or interface formation is detected in silicon nitride films deposited using the multi-deposition technique. This technique is applied to deposit pad silicon nitride with an edge-thin thickness profile, and is incorporated into a planar CMOS shallow trench isolation integration scheme to improve post-CMP oxide step height uniformity.