Silicon nanoelectronics: Precise fabrication via a bottom-up approach

Abstract

This issue of JOM includes four articles on silicon nanoelectronics critically selected and reviewed by the Thin Films & Interfaces Committee of the Electronic, Magnetic, & Photonic Materials Division of TMS. Silicon nanoelectronics is the fi eld of silicon-based electronic devices whose properties are deliberately manipulated at the atomic level in an attempt to produce electronic devices on the nanometer (10m) scale. As the term suggests, silicon nanoelectronics is a subset of much broader nanotechnology with an emphasis on silicon and electronics at the nano (from the Greek word nanos, which means dwarf) level. Thus, size does matter, but this fi eld does not simply stand for miniaturizing electronic devices to the nano regime. Like emerging nanotechnology in general, silicon nanoelectronics is often viewed in light of a paradigm shift for how we deliberate about fabricating an electronic device. For example, instead of a conventional top-down approach used for many years in electronic device fabrication plants, some silicon nanodevices can now be fabricated by adopting a bottom-up approach (i.e., utilizing self-assembly of atoms into silicon nanostructures). This novel approach in electronics is considered a more precise technique of engineering such devices at the nano-level. In addition, silicon nanoelectronics may include revolutionary design, materials, and process research endeavors to achieve ever-increasing device density and performance targets using fi eldeffect transistors (FETs). Many of the requirements for future ultrafi ne devices (projected to be at the ~20 nm level within the next decade) do not have known solutions, indicating there is no guarantee that the historically triumphant FET scaling will continue its success by relying only on evolutionary approaches to device miniaturization. Progress in the fi eld of silicon nanoelectronics is being actively reported by many academic and governmental institutes and private corporations through publications and patents. As one can imagine, it would be a challenging task to review all of them. However, it was not too diffi cult for this committee to select the following four papers, which I hope will serve as valuable references for JOM readers. The fi rst paper, “The Development of Nanocrystalline Silicon for Emerging Microelectronic and Nanoelectronic Applications” by C.C. Striemer, R. Krishnan, and P.M. Fauchet from the University of Rochester presents an overview of nanocrystalline silicon fabrication technologies potentially advantageous for memory-device and single-electron transistor applications. The authors address key engineering challenges related to applying the bottom-up approach to assembling such devices beyond the laboratory environment. The second paper, “The Production and Electrical Characterization of Free-Standing Cubic Single-Crystal Si Nanoparticles” by S.A. Campbell, U. Kortshagen, A. Bapat, Y. Dong, S. Hilchie, and Z. Shen from the University of Minnesota presents a technique to synthesize free-standing cubic singlecrystal silicon nanoparticles in an aerosol which may be transferred onto a wafer to build devices. Campbell et al. also describe a methodology to characterize the silicon nanostructures utilizing a novel sample preparation technique. The third paper, “Interconnect Challenges for Nanoscale Electronic Circuits” by N. Srivastava and K. Banerjee from the University of California at Santa Barbara deals with various performance and reliability challenges related to nanoscale interconnects that serve as key components of an electronic device by connecting building blocks such as transistors. Along with addressing materials and design challenges for the interconnects associated with sub-100 nm FETs, they include brief discussions on emerging interconnect technologies such as three-dimensional interconnects, optical interconnects, and carbon nanotube interconnects. The fourth paper, “The Magnetic Field-Assisted Assembly of Nanoscale Semiconductor Devices: A New Technique” by S. Shet, V.R. Mehta, A.T. Fiory, M.P. Lepselter, and N.M. Ravindra from the New Jersey Institute of Technology and BTL Fellows, Inc. introduces a novel magnetic fi eld-assisted assembly technique that may have potential applications for the placement of nanostructures into receptor sites fabricated on semiconductor wafers. The authors present this technique by discussing its potential advantage as a cost-effective and reliable way of assembling nanodevices. The Thin Films & Interfaces Committee hopes that JOM readers will fi nd these four articles interesting and informative and, more importantly, will recognize that silicon nanoelectronics is an emerging fi eld with technological and economic innovations for the future.