Silicon nano-asperities: Morphological evolution and electrical properties of double-polysilicon interlayers

Abstract

Polysilicon/silicon-dioxide/polysilicon structures (double polysilicon) are grown by deposition of amorphous silicon followed by thermal oxidation and a final polysilicon deposition process. Correlation between the appearance of silicon nano-structures and surface morphology formed during the amorphous silicon deposition stage and the electrical characteristics of the double poly capacitor have been investigated. It is shown that the process parameters have a pronounced effect on the morphological properties of the film surface. Nanometric size asperities form during the amorphous silicon deposition stage. The density and height distribution of these asperities were found to depend on deposition temperature. Thermal oxidation of the amorphous layer resulted in the growth of a top oxide layer and crystallization of the bottom silicon film. This process results in an overall increase of the surface roughness and a pronounced decrease in the height of the nano-asperities. By HF-etching the oxidized film, the surface of the polycrystalline silicon is exposed. Following this etching process, the surface roughness increases, whereas the density and height of the nano-asperities decrease. A correlation between the height of asperities on the bottom amorphous silicon film (as well as roughness of this film) and the breakdown voltage of the double poly was found.