Silicon Dioxide with a Silicon Interfacial Layer as an Insulating Gate For Highly Stable Indium Phosphide Metal‐Insulator‐Semiconductor Field Effect Transistors

Abstract

A novel gate insulator consisting of silicon dioxide with a thin silicon (Si) interfacial layer has been investigated for high‐power microwave indium phosphide metal‐insulator‐semiconductor field effect transistors (MISFETs). The role of the silicon interfacial layer on the chemical nature of the interface was studied by high‐resolution x‐ray photoelectron spectroscopy. The results indicated that the silicon interfacial layer reacted with the native oxide at the surface, thus producing silicon dioxide, while reducing the native oxide which has been shown to be responsible for the instabilities in MISFETs. While a 1.2 V hysteresis was present in the capacitance‐voltage (C‐V) curve of the MIS capacitors with silicon dioxide, less than 0.1 V hysteresis was observed in the C‐V curve of the capacitors with the silicon interfacial layer incorporated in the insulator. MISFETs fabricated with the silicon dioxide in combination with the silicon interfacial layer exhibited excellent stability with drain current drift of less than 3% in 104 s as compared to 15–18% drift in 104 s for devices without the silicon interfacial layer. High‐power microwave MISFETs with gate insulators resulted in an output power density of 1.75 W/mm gate width at 9.7 GHz, with an associated power gain of 2.5 dB and 24% power added efficiency.