Signal Window Map--A New Analysis Tool for FeRAM

Abstract

The properties of a ferroelectric capacitor are usually described by a hysteresis curve. However for high density FeRAM there is hardly any chance to measure the hysteresis curves for all cells directly. The only information that can be obtained by testing FeRAMs is of a digital nature: a cell is passing or failing. In order to quantify the quality of each cell capacitor individually, a new signal window analysis method has been developed. During a READ access in FeRAM operating in ITIC mode the stored signal of a memory cell is usually coupled to a bitline and then compared to a reference (Takashima et al. [1]). In ordr to optimize the reference voltage signal distributions for 0 (non switching) and 1 (switching) data have to be measured for the whole memory array. The voltage difference between the 0 and 1 signal of each individual cell determines this cell's signal window. This signal window describes the quality of a memory cell and it is analog information about the memory cell's performance. Plotting each cell's signal window value in a bit map using different colors for different signal windows gives a very sensitive tool for the analysis of the spatial distribution of the signal window. Since cell signals are directly related to their hysteresis properties the signal window map also gives information about the hyteresis variations across the chip. In addition, circuit properties that affect signal as well as process influences can be seen easily in this picture. Using the signal window map for the analysis of signal affecting parameters like write-voltage or timing proved to be a very sensitive tool to distinguish the influence of these parameters. In sum this analysis method provides feedback for process and technology development as well as for circuit analysis.