Signal Integrity Design and Analysis of Silicon Interposer for GPU-Memory Channels in High-Bandwidth Memory Interface

Abstract

In this paper, for the first time, we designed and analyzed channels between a graphic processing unit and memory in a silicon interposer for a 3-D stacked high bandwidth memory (HBM). We thoroughly analyzed and verified the electrical characteristics of the silicon interposer considering various design parameters, such as the channel width and space, redistribution layer via, and under bump metallurgy pads. In particular, we also considered the meshed ground planes used for the proposed transmission lines, which are microstrip and strip lines. Signal integrity (SI) of the proposed channels in the silicon interposer was successfully analyzed and verified using a full 3-D electromagnetic solver and circuit simulations. Based on the extracted lumped circuit resistance, inductance, conductance and capacitance parameters, we thoroughly analyzed the channel characteristics and identified the parameters that dominantly affect SI in relation to each frequency range. From the analyzed insertion loss and far end crosstalk, we verified SI of the silicon interposer by eye-diagram simulations in terms of eye-height voltage and timing jitter in the time domain. In the worst case, the eye-height voltage and timing jitter of the proposed microstrip lines are 0.911 V and 36.8 ps, respectively, with 72 mV of signal coupling. The eye-height voltage and timing jitter of the proposed strip line are 0.887 V and 42.1 ps with 34 mV of single couplings. We show that the proposed channels of the silicon interposer can successfully transfer data at a 2-Gb/s data rate. Finally, we propose concepts and solutions for the next-generation HBM interface with higher data rates up to 8 Gb/s.