Signal Adaptive Pipelined Hardware Design of Time-Varying Optimal Filter for Highly Nonstationary FM Signal Estimation

Abstract

In this paper we develop a multiple-clock-cycle signal adaptive hardware design of an optimal nonstationary (time-varying) filtering system. The proposed design is based on the real-time results of time-frequency (TF) analysis and the estimation of instantaneous frequency (IF). It permits multiple detection of the local filter's region of support (FRS) in the observed increment of time, resulting in the efficient filtering of multicomponent frequency modulated (FM) signals. The proposed design takes a variable number of clock (CLK) cycles---the only necessary ones regarding the highest quality of IF estimation---in different TF points within the execution. In this way it allows the implemented system to optimize the computational cost, as well as the time required for execution. Further, the proposed serial design optimizes critical design performances, related to the hardware complexity, making it a suitable system for real-time implementation on an integrated chip. Also, by applying the pipelining technique, it allows overlapping between different TF points within the execution, additionally improving the time required for time-varying filtering. The design has been verified by a field-programmable gate array (FPGA) circuit design, capable of performing filtering of nonstationary FM signals in real-time.