Abstract

This work is an additional effort to improve the performance of a four-moduli set residue-based sign detector. The study proposes an arithmetic sign detector for the extended four-moduli set { 2 n − 1 , 2 n + 1 , 2 2 n + 1 , 2 n + k } , where n and k are positive integers such that 0 ≤ k ≤ n . The proposed arithmetic unit is built using carry-save adders and carry-generation circuits. When compared with the only sign detector available in the literature for a similar moduli set, the proposed one showed very slight reductions in area and power. However, it showed a huge reduction in time delay. Using very-large-scale integration tools, the presented sign detector achieved a reduction of (48.8–59.2)% in time delay.

Full Text
Paper version not known

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call