SiGe/SiGeC HBT technology

Abstract

A retrospective look at the development and production of SiGe HBTs reveals that significant challenges have been overcome to make SiGe now a mature technology. In this chapter, key developments including the SiGe epitaxial growth process, overall integration methods, and elimination of yield-limiting defects to enable production of highly integrated products have been presented. Optimising the interaction of the EPI layer with its surroundings has enabled the achievement of high bipolar device yield. Integration of HP SiGe HBT with CMOS logic and a host of passive devices has created technologies that are well suited for a broad range of HP communication products. Modular integration approaches, such as the base-after-gate approach, has simplified the development of SiGe HBT technologies. It is observed that use of a modular integration approach enables a quick migration to next generation and derivative technologies easily. Enhancements have been achieved primarily in cost reduction, increased integration, and application specific voltage/power requirements. Vertical SiGe HBTs compatible with SOI CMOS have been discussed. The unique feature of collector voltage pinning in thm Si film was discussed in depth, which gives rise to high breakdown voltage, high Early voltage, and low collector capacitance. The SOI device is promising for a better fT-BVceo trade-off than that from conventional collector scaling in bulk devices. The fabricated devices show the anticipated strong dependence of d.c. and RF characteristics on SOI substrate bias. IBM's and IHP's SiGe and SiGeC BiCMOS technologies that have driven the requirements for the most advanced communication applications have been discussed. As a TCAD example, process and device simulation results for a trench isolated double polySiGe HBT using the process simulator ATHENA and device simulator ATLAS towards SiGe/SiGeC technology development have been presented. Use of TCAD tools for the SiGe/SiGeC technology development is expected to offer the process and device designers significant advantages in time-to-market, cost, power and performance prediction.