Abstract

The realization of surface-channel SiGe PMOSFETs has been hindered by poor gate oxide quality. Although buried-channel SiGe PMOSFETs using thin Si cap layers can alleviate these problems, the reduction of effective gate capacitance is a drawback. There has been some success in the deposition of ultra-thin SiO/sub 2/ films directly on strained SiGe using remote plasma chemical vapor deposition (Sharma et al, 1999); however, high leakage currents due to direct tunneling in thin oxide films are still difficult to be overcome. In recent years, high dielectric constant (high-k) materials have gained significant attention as possible replacements for conventional Si oxide. In this study, Si and surface-channel SiGe PMOSFETs are successfully fabricated for the first time using ultra-thin ZrO/sub 2/ gate dielectric. The equivalent oxide thickness (EOT) of ZrO/sub 2/ films is 18.7 /spl Aring/ for SiGe PMOSFETs, and 17 /spl Aring/ for Si devices.

Full Text
Paper version not known

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call

Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.