SiGe and Ge on Insulator Wafers

Abstract

This paper discusses the options to boost performances of PMOS in Fully Depleted CMOS via introduction of a SiGe compressively strained layer, specifically studying thickness uniformity of such SiGe layers. In a second part we discuss GeOI substrates as a substrate of choice for Ge PFET / IIIV NFET co-integration for future CMOS nodes, and its possible manufacturing using condensation method.