Sidewall spacer layer engineering for improvement of analog/RF performance of nanoscale double-gate junctionless transistors

Abstract

We investigate the impact of sidewall spacers on the analog/RF performance of double gate junctionless transistors at channel length of 30 nm using extensive numerical device simulation. Furthermore, we report the performance of a common source amplifier built employing such devices. The simulation deck is calibrated with experimental results published elsewhere. The influence of spacer layers is analyzed in terms of the dielectric constant and spacer layer thickness. Our findings reveal that peak transconductance and peak intrinsic gain increase by 5.2 and 71.3 % for spacer dielectric constant k = 30 as compared to the respective value for k = 3.9 while peak unity gain cut-off frequency and maximum frequency of oscillations increase by 37 and 83.3 % for k = 3.9 compared with the value for k = 30. It is evident from our studies that peak transconductance, peak transconductance generation factor, peak gain and peak cut-off frequency increase by 13, 10, 27 and 20 %, respectively, for spacer length of 5 nm compared with the corresponding value for spacer length of 15 nm. Additionally, our analysis shows that the peak gain of a common source amplifier increases with higher value of load resistance and spacer dielectric constant while it reduces with a larger spacer length. Moreover, we present a comparison of various device parameters of JLTs associated with analog/RF performance and gain of the common source amplifier with the corresponding parameter obtained with undoped inversion mode transistors.