Side-Channel Masking with Pseudo-Random Generator

Abstract

High-order masking countermeasures against side-channel attacks usually require plenty of randomness during their execution. For security against t probes, the classical ISW countermeasure requires $$\mathcal{O}(t^2 s)$$ random bits, where s is the circuit size. However running a True Random Number Generator (TRNG) can be costly in practice and become a bottleneck on embedded devices. In [IKL+13] the authors introduced the notion of robust pseudo-random number generator (PRG), which must remain secure even against an adversary who can probe at most t wires. They showed that when embedding a robust PRG within a private circuit, the number of random bits can be reduced to $$\mathcal{\tilde{O}}(t^{4})$$ , that is independent of the circuit size s (up to a logarithmic factor). Using bipartite expander graphs, this can be further reduced to $$\mathcal{\tilde{O}}(t^{3+\varepsilon })$$ ; however the resulting construction is impractical. In this paper we describe a construction where the number of random bits is only $$\mathcal{\tilde{O}}(t^2)$$ for security against t probes, without expander graphs; moreover the running time of each pseudo-random generation goes down from $$\mathcal{\tilde{O}}(t^{4})$$ to $$\mathcal{\tilde{O}}(t)$$ . Our technique consists in using multiple independent PRGs instead of a single one. We show that for ISW circuits, the robustness property of the PRG is not required anymore, which leads to simple and efficient constructions. For example, for AES we only need 48 bytes of randomness to get second-order security ( $$t=2$$ ), instead of 2880 in the original Rivain-Prouff countermeasure. As a first feasibility result, we have implemented our countermeasure on an ARM-based embedded device with a relatively slow TRNG, and obtained a $$50\%$$ speed-up compared to Rivain-Prouff.