Abstract
A SiC trench MOSFET with a merged heterojunction diode is proposed and numerically analysed here. The merged heterojunction diode can effectively suppress the turn-on of the parasitic body diode in the proposed SiC trench MOSFET. In addition, a P + shield layer surrounding the gate oxide layer can dramatically alleviate the gate oxide corner from the concentration of the electric field and improve the static and dynamic performances of the proposed device. As a result, not only the breakdown voltage is increased by 24% but also the miller charge and the switching losses of the proposed structure are reduced by 43 and 48.6%, respectively, when compared with those of the conventional SiC trench MOSFET with a grounded P + shield layer. Moreover, the short-circuit capability and its failure mechanism are numerically studied for the proposed structure. Finally, a feasible fabrication procedure is provided to realise the fabrication of this new device.
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