Abstract

The main factor still hindering a wide industrial adoption of SiC power MOSFETs is essentially a global reduced ruggedness in comparison to their Si counterparts. The proposed gate driving architecture leverages fault-induced gate voltage disturbances and enhances them to facilitate their detection through two dedicated commutated gate resistors. This approach combines switching dynamics and enhanced ON-state fault sensibility. This architecture, affording innovative short-circuits and overload detections, as well as gate-oxide integrity monitoring, was validated on a 600 V short-circuit power test bench using commercial 1200 V/36 A SiC MOSFETs.

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