SiC Planar MOSFET Structures

Abstract

In the previous chapters, it was demonstrated that the maximum operating frequency of high voltage bipolar silicon power devices is limited by the power dissipation due to their slow switching transients. The rate of rise of the voltage and rate of fall of the current during the turn-off process in these devices is slowed down by the presence of the large amount of stored charge in the drift region. Consequently, high voltage silicon carbide unipolar power MOSFET devices are a very attractive alternative to silicon bipolar power devices [1, 2]. Silicon carbide power device structures have been discussed in detail in a previous book [3]. In that book, it was shown that the conventional planar power D-MOSFET structure, developed and widely utilized for silicon, is not suitable for the development of silicon carbide devices. Two problems are encountered when utilizing the conventional power D-MOSFET structure for silicon carbide. The first problem is the much larger threshold voltage required to create an inversion layer in silicon carbide due to its much greater band gap. The doping concentration required in the P-base region to achieve a typical threshold voltage of 2 V is so low that the device cannot sustain a high blocking voltage due to reach-through of the depletion layer in the base region. The second problem is the very high electric field generated in the gate oxide because the electric field in the silicon carbide drift region under the gate is an order to magnitude larger than for silicon devices. This leads to rupture of the gate oxide at large blocking voltages.