SiC MOSFETs capacitance study

Abstract

SiC MOSFTEs are widely used nowadays for a large number of power applications. Even though they are more performant than their Silicon counterpart, they suffer from some issues which are still unsolved. Among these, the high traps concentration existing at the SiC/SiO2 interface is one of the main concerns while evaluating the device performance. To this aim, the characterization of such interface is of paramount importance. Capacitance versus voltage (C–V) curves are fast and non-destructive measurements which can give an insight in the device physics. They are usually performed with the driving signal imposed on the Gate, while Drain and Source are grounded. However, measuring the capacitance in alternative configuration can provide additional information about the traps distribution existing in the mentioned interface. In this work, a numerical study is performed on the capacitance measured in the following configurations: (i) floating Source; (ii) floating Drain and (iii) positive biased Drain. The study has been performed at different temperature. The numerical results are enforced by experimental findings.