SiC device technology: remaining issues

Abstract

Some of the key remaining issues facing SiC device technology for power devices and high temperature devices are discussed. Research on improving the oxide/SiC interface quality has shown that a low temperature re-oxidation step yields interface trap densities of 1 × 10 11 cm −2 eV −1 , resulting in a high SiC MOSFET channel mobility of 72 cm 2 /V-sec. Device lifetimes for SiC n-channel MOSFETs have been increased to as much as 5 years at 350 °C, and time-dependent dielectric breakdown of oxides on p-type SiC have lifetimes > 700 years at 2 MV/cm and 350 °C. Sheet resistivities for p + of < 10 kΩ/sq. and p-type contact resistivities less than 10 −5 Ω-cm 2 have been obtained using high temperature Al + ion implantation processes. These processes have been used to fabricate the first SiC CMOS circuits, with an operational amplifier having a gain > 10 5 . High voltage termination techniques have improved Schottky diode yield, as well as that of mesa devices such as 4.2 kW, 700 V thyristors. The defect densities of SiC substrates has also been improved, with recent 4H-SiC wafers having a micropipe density of 1.8 cm −2 .