Shuttle Communication Systems Compatibility and Performance Testing

Abstract

The Shuttle communications system consists of major space and ground elements. The space elements include the Orbiter, Tracking and Data Relay Satellite, payload and extravehicular astronaut communications subsystems. The Spaceflight Tracking and Data Network, relay satellite ground segment, and the Air Force Satellite Control Facility make up the major ground elements of the communications system. The compatibility and performance of each of these major elements functioning as a complete system must be certified prior to operational missions. Unique Shuttle communication channels employing spread spectrum techniques, high rate data (50 Mbits/s), convolutional encoding, and unbalanced quadriphase modulation must be evaluated on an end-to-end RF (radio frequency) system basis. To accomplish the necessary communication system compatibility and performance tests, NASA has established the ESTL (Electronic Systems Test Laboratory) at the Lyndon B. Johnson Space Center. This paper discusses the Shuttle communication systems compatibility and performance testing which is being accomplished at the ESTL. The system test philosophy for the complex communications channels is described in terms of the major phases which include early breadboard system design evaluation tests, system verification tests with prototype hardware and system certification testing with qualifiable (flight) hardware. The system hardware configuration, facility requirements, test and evaluation techniques and operational approaches required to accomplish each major phase of testing are reviewed. Results of recently completed space-to-space and space-space-to-ground system tests are presented. Test techniques and measurement accuracies proven over 10 years of system evaluation experience unique to the ESTL are reviewed. Techniques used in relating experimental system performance and predicted system performance (based on hardware math models), and conclusions regarding effectiveness of system level testing of such complex hardware are addressed.