Abstract
Phase change memory (PCM) has many advantages over the traditional DRAM technology, hence it becomes a promising candidate for main memory. Multi-level cell (MLC) PCM has the benefits of higher capacity and lower cost-per-bit due to store multiple bits in a single cell. However, MLC PCM employs an iterative write scheme, which is precise, reliable but slow, incurring adverse impact on the system performance. In this work, we analyzed the characteristics of the SET pulse in PCM, and modeled the relationship of the resistance and the SET pulse in MLC. Based on the analysis, we proposed a short SET pulse as an iterative pulse for MLC, so as to accelerate the MLC PCM write operation without the reliability degradation. Experimental results show that the Short-SET write scheme could effectively alleviate the long write problem of MLC PCM and improve the system performanceby 90%. Meanwhile, the write power is reduced by 23%.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
