Short-channel transport behavior in scaled 25-nanometer GaAs/AlGaAs heterostructure field effect transistors

Abstract

Ultra-short channel AlGaAs/GaAs heterostructure field effect transistors with gate lengths ranging up to 20 nm were fabricated using an electron-beam lithography process in order to examine the fundamental limitation of transistor scaling. An improvement in the transconductance caused by electron velocity overshoot starts to occur in our devices with sub-70-nm gate lengths, which is suppressed partially by a parasitic gate-fringing at a reduced gate aspect ratio. However, we find that the transconductance starts to drop for gate lengths below 40 nm and that the enhancement in the transconductance caused by the velocity overshoot is limited with further scaling. To investigate the velocity overshoot and its’ degradation, we used a transport model based on the Retarded Langevin equation (RLE). The average transient velocity obtained by using the RLE shows reasonable agreement with the effective electron velocity extracted from the experimental results by using an analytical approximation. Also, the inverse-linear proportionality of log(I DS) to {ie1} (based on the WKB approximation) demonstrates the existence of short-channel tunneling at very small gate lengths (smaller than 40 nm in our devices).