Abstract
This paper presents the device design of short channel MOS-FET's based on accurate two dimensional analysis and some experimental results of related small size devices. Threshold voltage lowering effects in short channel devices are computed and the experimental structure which is fabricated using a Si gate and ion-implantation technology is determined. Experimental results verify the newly predicted short channel effects; a reduced substrate bias effect and a poor tailing drain current; which are obtained through the two dimensional analysis. The fabricated ring oscillator displays high circuit performance of the delay and power products of 0.12 pJ, thus opening the way to sub-pJ LSI circuits.
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