Shifted Leakage Power Characteristics of Dynamic Circuits Due to Gate Oxide Tunneling

Abstract

The subthreshold and gate oxide leakage power characteristics of domino logic circuits are evaluated in this paper. The preferred input vectors and node voltage states are identified to minimize the total leakage power consumption in the sleep mode. New low leakage design guidelines based on the results are presented. Previous studies indicate that a discharged dynamic node voltage state with high inputs is preferable to reduce the subthreshold leakage power consumption in an idle dual threshold voltage domino gate. However, the gate oxide leakage is ignored in the previous studies. The significantly increased gate dielectric tunneling current, as described in this paper, shifts the leakage power characteristics of dynamic circuits in the sub-65nm CMOS technologies. Contrary to the previously published techniques in older technologies, a charged dynamic node voltage state with low inputs is preferred for reducing the total leakage power consumption in the wide fan-in dual threshold voltage domino gates. Similarly, a charged dynamic node voltage state with low inputs is preferred for lowering the leakage power consumption in all types of low threshold voltage domino gates in a 45nm CMOS technology