Sharing of Compressed Tests Among Logic Blocks

Abstract

In a design that consists of several logic blocks, each logic block may be tested separately using its own compressed test set and on-chip decompression logic. The decompression logic is typically based on a linear circuit, such as a linear-feedback shift register (LFSR), and tests are compressed into initial states (seeds). This article observes that even if different LFSRs of different lengths are used for different logic blocks, there is flexibility to select compressed tests that can be shared among the logic blocks. This article describes a test compaction procedure that accepts compact compressed test sets computed for the logic blocks individually. The procedure combines the test sets into a single test set and optimizes it considering all the logic blocks together. This is important for applications where storage of tests is a bottleneck. Experimental results are presented to demonstrate the effectiveness of the test compaction procedure when groups of benchmark circuits are considered as logic blocks in the same design. A procedure for constructing groups with significant sharing of compressed tests is also discussed.