Abstract
Several abstract models of parallel computation have been developed and studied by the computer science and parallel processing communities [1, 2]. The shared memory models are among the most computationally powerful of these models. They benefit from substantial theoretical foundations, and many algorithms have been mapped onto these models in order to characterize theoretically optimum parallel performance. A number of attempts have been made to develop electronic parallel architectures based on the shared memory model. Most of them have been unsuccessful, primarily due to the complexity of the interconnection network hardware and its associated control.
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