SHAPE RECOGNITION USING A FIXED-SIZE VLSI ARCHITECTURE

Abstract

Shape recognition is an important research area in pattern recognition. It also has wide practical applications in many fields. An attribute grammar approach to shape recognition combines both the advantages of syntactic and statistical methods and makes shape recognition more accurate and efficient. However, the time complexity of a sequential shape recognition algorithm using attribute grammar is O(n3) where n is the length of an input string. When the problem size is very large it needs much more computing time, therefore a high speed parallel shape recognition is necessary to meet the demands of some real-time applications. This paper presents a parallel shape recognition algorithm and also discusses the algorithm partition problem as well as its implementation on a fixed-size VLSI architecture. The proposed algorithm has time complexity O(n3/k2) if using k×k processing elements. When k=n, its time complexity is O(n). The experiment has been conducted to verify the performance of the proposed algorithm. The correctness of the algorithm partition and the behavior of the proposed VLSI architecture have also been proved through the experiment. The results indicate that the proposed algorithm and the VLSI architecture could be very useful to imaging processing, pattern recognition and related areas, especially for real-time applications.