Abstract
The Spiking Neural P (SN P) system is defined as a type of parallel computing mechanism bio-inspired by the behavior of the soma. Several authors have been employing these systems in order to create efficient arithmetic divisor circuits exploiting at maximum their intrinsic parallel processing. However, the current neural divisors expend a large amount of neurons with complex spiking rules to synchronize the input information to be processed by the soma. This work proposes a compact neural divisor that uses eight neurons and two type spiking rules per neuron. In addition, the proposed circuit includes the dendrite’s behavior as feedback connections, dendritic delays, reduction in the dendrite length and dendritic pruning into the conventional SN P systems in order to simplify the synchronization of the neural processing carried out by the soma. The results show that the proposed neural divisor can be implemented in embedded neuromorphic circuits. This, potentially allows its use in portable applications such as vision processing systems for mobile robots and cryptographic systems for mobile communication devices.
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