Shallow Trench Isolation for the 45-nm CMOS Node and Geometry Dependence of STI Stress on CMOS Device Performance

Abstract

In the present work, a high aspect ratio process (HARP) using a new O3/TEOS based sub atmospheric chemical vapor deposition process was implemented as STI gapfill in sub-65-nm CMOS. Good gapfill performance up to aspect ratios greater than 10:1 was demonstrated. Since the HARP process does not attack the STI liner as compared to HDP, a variety of different STI liners can be implemented. By comparing HARP with HDP, the geometry dependence of nand p-FET performance due to STI stress is discussed