Shadow Stack Scratch-Pad-Memory for Low Power SoC

Abstract

In many embedded system, researches focus on how to use on-chip memory, like SPM, to reduce the energy consumption generated by off-chip memory, such as SDRAM or DRAM. They put the often use instructions and important data into on-chip memory to reduce the power because off-chip memory consumes a large of energy than on-chip memory. However, stack is a key factor that impacts the power consumption, since when function is called, the passing parameter, local variables and temporary data will use stack. We organize a shadow stack scratch-pad memory which operation behavior is somewhat like Cache, to store the stack data to reduce the stack access of off-chip memory. This memory architecture is called S3PM. The S3PM has two segments to remap the off-chip memory, leading CPU to access the S3PM when the access address is in the range of remapped area byS3PM. The paper proposes a novel memory subsystem architecture which constituted by the off-chip SDRAM, on-chip S3PM and traditional SPM. The S3PM is used to remap the stack off-chip memory which address is accessed high frequently while traditional SPM is used to store instruction and data. The results shows that the S3PM can reduce many energy but using a little size of on-chip memory.