Settling Time and Noise Optimization of a Three-Stage Operational Transconductance Amplifier

Abstract

This paper presents the design and optimization of a nested-Miller compensated, three-stage operational transconductance amplifier (OTA) for use in switched-capacitor (SC) circuits. Existing design methods for three-stage OTAs often lead to sub-optimal solutions because they decouple inter-related metrics like noise and settling performance. In our approach, the problem of finding an optimal design with the best total integrated noise and settling time has been cohesively solved by formulating a nonlinear constrained optimization program. Equality, inequality, and semi-infinite constraints are formed using closed form symbolic expressions obtained by a closed loop analysis of the SC gain stage and the optimization program is solved by using the interior-point algorithm. For the optimization routine, there is no need to interface with a circuit simulator because all significant device parasitics are included in the model. The optimization and modeling steps are general in nature and can be applied to any amplifier or filter topology. Simulation results show that a 90-nm prototype amplifier achieves a $\pm 0.1{\hbox{\%}}$ dynamic error settling time of 2.5 ns with a total integrated noise of 240 $\mu {\rm V}_{\rm rms}$ , while consuming 5.2 mW from a 1-V power supply.