Setting quality control requirements to balance between Cycle Time and Yield in a semiconductor production line

Abstract

We consider a semiconductor production line in which production stations are afflicted by a defect deposition process and immediately followed by an inspection step. We propose to integrate operational aspects into quality considerations by formulating a Cycle Time (CT) versus Yield trade off. We connect the two performance measures through the determination of the limit for defects at the inspection step. We extend former results to a tandem production line and present an optimal greedy algorithm that provides the Pareto-optimal set of Upper Control Limit (UCL) values for the line. The obtained model enables decision makers to knowingly sacrifice Yield to shorten CT and vice versa.