Session 6: Parallel implementations of HEVC and FFT for embedded multi-/manycore systems

Abstract

For many years, following the ever-increasing number of transistors per chip, advances in computer architecture mostly consisted of adding complex mechanisms to mono-core processors to improve their computing performance. In the last decade, the continuous growth of computing performance was supported by the introduction of multi-core architectures, first for high-performance computing, then in mainstream desktop CPUs, and now in smartphones and embedded systems. Today, one of the main challenges researchers must overcome is finding how to implement applications that fully exploit the computing performance offered by these multicore architectures with tens, hundreds, and soon thousands of cores. In this session, parallel implementations of State-of-the-Art signal and video processing applications on multi and manycore architectures are presented. The first two talks of this session focus on implementation of HEVC video encoder on modern architecture. The implementation of intra encoding algorithms of HEVC on heterogeneous multicore architectures will be presented by the Fraunhofer HHI, and the optimization of the complexity-quality tradeoff of hardware-accelerated HEVC coding will be presented by the Politecnico di Torino. Finally, an implementation of the Fast Fourier Transform on a manycore embedded system will be presented as a result of collaboration between Kalray, INSA Rennes, and the Auckland University of Technology.