Session 21 Overview: RF Potpourri

Abstract

Oscillators are ubiquitous and critical blocks in all wireless transceivers, whether UWB, or based on sinusoidal carriers. There seems to be no end to the exploration of creative ways to improve oscillator performance in any one of several dimensions. Paper 21.1 describes a circular-geometry 5.3GHz oscillator that uses high-Q slab inductors to achieve a phase noise of -147.3dBc/Hz at 10MHz offset, while drawing 10mA from a 1.4V supply. A tunable version of this oscillator consumes 12mA from 1.8V, achieves a -142.2dBc/Hz phase noise at a 10MHz offset from a 5.4GHz carrier frequency, and possesses an 8% tuning range. Both oscillators are implemented in a 0.18µm CMOS technology. Paper 21.2 describes a circular oscillator that employs standing waves on a ring transmission line. A 10GHz prototype realized in a SiGe bipolar technology exhibits a phase noise of -110dBc/Hz at a 1MHz offset, while drawing 1.95mA from a 1.5V supply. Even-mode suppression assures oscillation at the desired mode frequency. Paper 21.10 describes a 1.7GHz VCO intended for use in direct-conversion CDMA receivers. It possesses a tuning range of 350MHz, using a grounded-junction-diode varactor. The CMOS oscillator exhibits a phase noise of -134dBc/Hz at an offset of 900kHz, and a DC power-supply pushing coefficient below 25kHz/V. Ultrawideband (UWB) systems have received increasing attention in recent years, as an alternative means to increase data rates. Papers 21.3 and 21.4 describe low-noise amplifiers for operation in the UWB band spanning 3.1 to 10GHz. The CMOS LNA presented in Paper 21.3 satisfies Fano's broadband matching criteria with a three-section bandpass Chebyshev structure at the input to obtain the requisite bandwidth. Fabricated in a 0.18µm process, the LNA exhibits a power gain of 9.3dB, a noise figure of 4dB, an IIP3 of 6.7dB, and a power consumption of 9mW. Paper 21.4 also employs Fano's matching methods to provide a broadband input match. The SiGe amplifier provides 22dB peak gain, 2.5dB noise figure, and a 0dBm IIP3 at 5GHz. The remarkable growth of wireless LAN (WLAN) systems has stimulated consideration of ever-higher carrier frequencies for higher data rates, as well as for improved spectral re-use to mitigate a putative shortage of spectrum. Of growing interest are WLAN transceivers operating in the 17GHz ISM band. Paper 21.5 presents a 13GHz ∆Σ fractional-N PLL for WLAN applications in that frequency band. The synthesizer includes a VCO, quadrature divider, multimodulus prescaler, phase-frequency detector, second-order ∆Σ modulator, charge pump and loop filter. Built in a 0.13µm CMOS technology, it consumes 60mW from a 1.5V supply. Paper 21.6 describes a 17GHz image-reject downconversion block implemented in a SiGe-BiCMOS technology. This front-end circuit consists of a low-noise amplifier, doubly-balanced mixers, and a subharmonic-locked quadrature local oscillator. The chip features monolithic coupling transformers, and consumes 62.5mW using a 2.2V supply. Silicon's suitability for operation at millimeter-wave frequencies is amply demonstrated by circuits functioning at nearly 40GHz. Paper 21.7 presents a fully-integrated 24GHz phased-array receiver, each channel of which possesses a gain of 43dB, a noise figure of 8dB, and an IIP3 of -11dBm. The 8-channel array has a beamforming resolution of 22.5 O , a gain of 61dB, and produces a peak-to-null ratio of 20dB. The SiGe BiCMOS chip consumes 29mA from a 2.5V supply. Paper 21.9 describes a VCO operating from 35.2 to 37.6GHz, using cascaded emitter followers in a SiGe bipolar technology. The oscillator uses an on-chip LC tank, and achieves a phase noise of -105dBc/Hz at a 2MHz offset. Other marked performance improvements may be provided at the system level by the use of some form of diversity. Paper 21.8 describes a phase shifter that is of particular value in combining signals from multiple antennas. The judicious use of negative resistance reduces the losses in passive phase shifters to enable operation over a 2.27 to 2.45GHz frequency span. The shifter exhibits a phase-control range in excess of 100 O , and is implemented in a 180nm CMOS technology. Simply achieving some gain at high frequency is not sufficient, of course. Linearity must be maintained throughout the signal-processing chain. Paper 21.11 describes a distortion-cancellation technique that reduces the IM3 products generated by a SiGe mixer by 18dB. The prototype exhibits an IIP3 of 10dBm, a gain of 8.7dB, and a noise figure of 9.8dB, while consuming 30mW from a 2.9V supply.