Abstract
There are six papers in this session on the integration of high-k/metal gates in a CMOS flow. High-k metal gate stacks have now been introduced in production for the 45nm node. Work function setting and control are still critical and will need further improvement and understanding in order to continue scaling the threshold voltage as well as fabrication of multi Vt devices using high-k metal gate stacks. This session includes an invited paper that describes chemical mechanical polishing as a critical technology enabler for the integration of metal gate electrodes with high-k materials in a gate last flow and several papers on work function control and setting using various approaches. The contributed papers provide basic understanding on the effects of various metal oxides on the SiO 2 /high-k interface, EOT scaling and work function control.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
