Abstract
In the design of synchronous digital counters the carry chain which starts from the least significant digit determines the maximum clock speed. Various schemes for implementing the carry calculation have been proposed to minimise the time of that computation. The author describes a new technique which uses additional state bits to aid in the carry calculation. This is shown to give a useful increase in clock speed over conventional combinational logic based carry lookahead techniques. The technique is also applicable to general finite state machines.
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