Abstract
Existing analyses of the sensitivity of threshold-logic gates to input voltage and component tolerances are, in general, complex. It is here shown that the sensitivity performance of practical gate realisations may be related very simply to the Chow parameters of the gate.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.