Sensitivity evaluation of global resonant H-tree clock distribution networks

Abstract

A sensitivity analysis of resonant H-tree clock distribution networks is presented in this paper for a TSMC 0.18 ?m CMOS technology. The analysis focuses on the effect of the driving buffer output resistance, on-chip inductor and capacitor size, and signal and shielding transmission line width and spacing on the output voltage swing and power consumption. A two level resonant H-tree network exhibits low sensitivity to these variations.