Abstract
In this letter, a simple but effective sense-amplifier driving circuit using adaptive delay line is proposed to suppress a high current peak occurring in enabling sense amplifiers at a fast Process-VDD-Temperature (PVT) condition. And, this circuit also can improve a slow enabling time of sense amplifiers at a slow PVT corner. This new circuit is verified in recent 0.18-µm DRAM technology, where the variations in the sense-amplifier enabling time and peak current are suppressed from 72% to 1% and 240% to 28%, respectively, compared with the previous sequential sense-amplifier driving circuit.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
