Semi-additive patterning process based fabrication of miniaturized, package-embedded high conversion ratio inductors for DC-DC converters

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• A scalable semi-additive patterning process for fabrication of highly miniaturized toroidal inductors irrespective of bulk conductivity of the magnetic core. • Double sided, 3-step drilling for less tapered through substrate features. • Dielectric slot filling requires higher vacuum time, pressure, and pressure time. • No photoresist seepage into through substrate vias with roll lamination. Many data centers currently operate at low power efficiencies (∼75%) because of the many voltage conversions necessary to step down inputs from 48 V to 1 V. This voltage step-down is accomplished in the Power System-on-Chip (PwrSoC) package, which contain large quantities of surface mount inductors. However, surface mount inductors are large in area and require long power delivery networks to supply the voltage to the PwrSoC, thereby leading to interconnection losses and reducing overall system efficiency. Miniaturizing these inductors could place them nearer to the PwrSoC. Miniaturized and embeddable solenoid and toroidal inductors can be built from magnetic substrates using patterned copper windings created from through substrate vias and micropatterning. However, to achieve inductances close to SMTs, magnetic substrates must be thick or have large lateral footprints. Furthermore, the magnetic flux leakage must be minimized between inductors. This work will elucidate the challenges of dielectric filling of through substrate slots, laser drilling of slots and vias in different substrates, and dry film photoresist lamination that will enable complete copper windings. This paper presents the process flow, challenges, and redressal of these challenges to build miniaturized, embedded inductors that have previously been introduced by our research team.